What is a Decoder?
A decoder is a higher-level building block commonly used in digital circuits. A decoder decodes an input code into a set of output lines.
An n-to-m decoder has n inputs and m outputs where m ≤ 2n. The most common type is the n-to-2n decoder, which activates exactly one of its 2n outputs based on the binary value of its n inputs.
2-to-4 Decoder
The simplest practical decoder has 2 inputs and 4 outputs. The input lines represent a 2-bit binary number, and the corresponding output line becomes active.
Block diagram: 2 inputs select which of 4 outputs is active
Truth Table
The truth table shows that output Di is active (equals 1) when the binary value of the inputs equals i. Hover over rows to see the pattern.
| Inputs | Outputs | |||||
|---|---|---|---|---|---|---|
| A | B | D0 | D1 | D2 | D3 | |
| 0 | 0 | 1 | 0 | 0 | 0 | |
| 0 | 1 | 0 | 1 | 0 | 0 | |
| 1 | 0 | 0 | 0 | 1 | 0 | |
| 1 | 1 | 0 | 0 | 0 | 1 | |
Observe: When inputs equal binary i, output Di is active.
For example, when A=1 and B=0, the binary value is 102 = 2, so D2 is active. This pattern makes decoders perfect for address decoding—selecting one device out of many based on an address.
Internal Design
A decoder is built using AND gates and NOT gates (inverters). Each output corresponds to one minterm of the input variables. A minterm is a product (AND) of all variables where each variable appears exactly once, either in true or complemented form.
Each output is an AND gate. Inputs are inverted as needed to match the minterm.
The internal design requires:
- n NOT gates to generate the complement of each input
- 2n AND gates with n inputs each, one for every output
Gate-Level Implementation
Here is the complete gate-level schematic for a 2-to-4 decoder. The two NOT gates at the left generate A' and B'. Each AND gate receives the appropriate combination of true and complemented inputs.
Gate-level implementation showing NOT gates generating complements, AND gates producing outputs
Try It Yourself
Interact with the circuit below. Click the input bits to toggle them and observe which output becomes active. Notice how exactly one output is always high.
Decoders with Enable
Most commercial decoders include one or more enable inputs. When the enable is inactive, all outputs are forced to 0, regardless of the data inputs. This feature is essential for building larger decoders and for controlling when the decoder operates.
| Enable | Inputs | Outputs | |||||
|---|---|---|---|---|---|---|---|
| E | A | B | D0 | D1 | D2 | D3 | |
| 0 | X | X | 0 | 0 | 0 | 0 | |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | |
| 1 | 0 | 1 | 0 | 1 | 0 | 0 | |
| 1 | 1 | 0 | 0 | 0 | 1 | 0 | |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | |
When E=0, all outputs are 0 regardless of A and B (X = don't care)
Larger Decoders
Decoders scale exponentially: adding one input bit doubles the number of outputs. A 3-to-8 decoder has 3 inputs and 8 outputs. Common sizes include:
3-to-8 decoder: 3 inputs, 8 outputs (23 = 8)
Building Larger Decoders
Larger decoders can be constructed by combining smaller decoders. To build an (n+1)-to-2n+1 decoder from two n-to-2n decoders:
- Use the extra input bit to enable one decoder and disable the other
- Connect the remaining n inputs to both decoders in parallel
- The enabled decoder produces outputs 0 to 2n-1 or 2n to 2n+1-1
3-to-8 decoder built from two 2-to-4 decoders using C as enable selector
When C=1, the top decoder is enabled and produces D0–D3. When C=0, the bottom decoder is enabled and produces D4–D7.
Decoders as Function Generators
A decoder with an OR gate can implement any Boolean function. Since each decoder output represents one minterm, you can OR together the outputs corresponding to the minterms where the function equals 1.
Example: Implement F(A,B) = A'B + AB' (XOR function)
The minterms where F=1 are: m1 (A'B) and m2 (AB')
OR the decoder outputs corresponding to minterms where the function equals 1.
This is a powerful technique: an n-to-2n decoder plus one OR gate can implement any function of n variables. For functions with many minterms, this may require fewer gates than a direct implementation.
Applications
Memory Address Decoding
Select which memory chip or register responds to a given address. A 10-bit address decoder can select one of 1024 memory locations.
Seven-Segment Displays
Convert BCD digits into signals that light up display segments. A BCD-to-7-segment decoder is a specialized 4-to-10 decoder.
Instruction Decoding
CPUs decode opcode bits to determine which operation to execute. A 6-bit opcode field can select one of 64 different operations.
Demultiplexing
Route a single input signal to one of many output channels. A decoder with an enable input acts as a demultiplexer.
Keyboard Encoding
Identify which key is pressed in a keyboard matrix by decoding row and column addresses.
Timing and Sequencing
Generate timing signals by decoding counter outputs. Each count value activates a different control signal.
Summary
- A decoder converts an n-bit binary input into 2n output lines
- Exactly one output is active at any time (one-hot encoding)
- Built from n NOT gates and 2n AND gates, one per minterm
- Enable inputs allow the decoder to be disabled (all outputs = 0)
- Larger decoders are built by cascading smaller ones using enable inputs
- Any Boolean function can be implemented with a decoder and an OR gate
- Essential for address decoding, instruction decoding, and demultiplexing